Simulation setup for Opamp characterizations

Of course running a simulation without any setting any options/variables and getting any output data is neither fun nor productive. Hence, we will introduce these aspects into our OCEAN Script. Before that, it is necessary to establish some context for a typical test setup for an single-end opamp.

Simple simulation setup for Opamp characterization.

The DUT (Device Under Test) - the opamp has self-explanatory pins of VIN, VIP, OUT, VDD, GND, and IBIAS. It also has an instant name of I1, in this circuit.

Voltage source V0 supplies power for the whole opamp via net and pin VDD. DC current source IB sets biasing current to the opamp. Value for supply voltage - VDD = 1.8V, is typical for design in 0.18um CMOS process. We choose our biassing current IB = 10uA.  

Sinusoidal voltage source V1 connects to pin VIP. This provides AC input signal with suitable DC biasing for VIP. This voltage is usually set to VDD/2 = 0.9V, in this circuit.

Capacitor C1 and inductor L1 short VIN and OUT at DC and disconnect them at higher frequency. As a result, the config forms an unity gain buffer at DC, hence it sets a bias voltage to VIN which is the same with that of VIP. For this purpose, the values of C1 and L1 are chosen to be huge, for example 10F and 1GH.

Capacitor CL is the load the opamp drives. Its value is usually in pF range, say 5pF.

With this test setup, we will be able to estimate some major specifications of the opamp as follows: Open loop gain - OLGain, gain bandwidth - GBW, phase and gain margin - PM and GM, and current consumption - ID.

From these data, a simplified figure of merit - FOM of the opamp can be calculated. FOM estimates how much gain banwidth the opamp has with certain load capacitance while it burns certain amount of current.

That's it for now.

PS: I created a simple component template for circuit schematic drawing here. Feel free to use it.